1. Field of the Invention
The invention relates to a semiconductor memory device, particularly, a semiconductor memory device having a plurality of electrically data erasable and writable nonvolatile memory cell transistors.
2. Description of the Related Art
Recently, the nonvolatile memory is used not only for consumer goods such as a mobile, a digital camera and the like but also for on-vehicle, aerial or medical equipments, an ID card and the like which require high reliability in data storage.
The EEPROM (Electronically Erasable and Programmable Read Only Memory) is known as a general nonvolatile memory. This stores binary or multivalued digital data depending on whether or not a predetermined charge amount is accumulated in a floating gate and reads the digital data by sensing the change of a channel conductance according to this charge amount. This EEPROM includes a stacked gate type EEPROM having a structure where a floating gate and a control gate are sequentially stacked on a semiconductor substrate and a split gate type EEPROM having a structure where a floating gate and a control gate face a channel of a semiconductor substrate.
FIG. 3 is a cross-sectional view showing one memory cell transistor MT of the split gate type EEPROM. An n+-type drain 102 and an n+-type source 103 are formed on a front surface of a P-type semiconductor substrate 101 at a given distance from each other, and a channel 104 is formed therebetween. A floating gate 106 is formed on a portion of this channel 104 and a portion of this source 103 with a gate insulation film 105 being interposed therebetween. An insulation film 107 thicker than the gate insulation film 105 is formed on the floating gate 106.
A tunnel insulation film 108 is formed covering the side surface of the floating gate 106 and a portion of the upper surface of the thick insulation film 107. A control gate 109 is formed on the tunnel insulation film 108 and a portion of the channel 104.
The operation of the memory cell transistor MT having this structure is as follows.
First, when data “0” is written, a predetermined voltage is applied to the control gate 109 and the P-type semiconductor substrate 101 (e.g. 0V to the P-type semiconductor substrate 101 and 2V to the control gate 109) and a high voltage (e.g. 10V) is applied to the source 103 to flow a current through the channel 104, and thereby channel hot electrons are injected into the floating gate 106 through the gate insulation film 105. The channel hot electrons injected into the floating gate 106 are held in the floating gate 106 as electric charge.
On the other hand, when the data “0” stored in the memory cell transistor MT is erased, the drain 102 and the source 103 are grounded and a predetermined high voltage (e.g. 13V) is applied to the control gate 109 to flow a Fowler-Nordheim tunneling current through the tunnel insulation film 108, and thereby electrons accumulated in the floating gate 106 are extracted to the control gate 109. By this erasing, the digital data stored in the memory cell transistor MT turns to “1”.
When the data stored in the memory cell is read out, a predetermined voltage is applied to the control gate 109 and the drain 102 (e.g. 3V to the control gate 109 and 1V to the drain 102). Then, a cell current Ic flows between the source and the drain according to the charge amount of electrons accumulated in the floating gate 106. When the data “0” is already written, the threshold of the memory cell transistor MT is high and thus the cell current Ic usually reduces to about 0 μA. When the data “1” is already written, the threshold of the memory cell transistor MT is low and thus the cell current Ic usually increases to about 40 μA.
Then, the data is judged to be “0” or “1” by comparing this cell current Ic with a reference current with a given sense amplifier. For example, in the case of the reference current=20 μA, when the cell current Ic has the current amount of 20 μA or more the sense amplifier senses it and outputs a voltage value of 5V (the data “1”), and when the cell current Ic has the current amount of 20 μA or less the sense amplifier outputs a voltage value of 0V (the data “0”).
The described technique is described in the Japanese Patent Application Publication No. 2000-173278.
As described above, in the memory cell transistor MT, it is necessary to apply a high voltage when data is written and erased. The circuit structure of such a semiconductor memory device will be described referring to FIG. 4.
A high voltage generation circuit 1 generates a high voltage HV by boosting a supply voltage Vcc (e.g. 3V) inputted to the semiconductor memory device. A high voltage switching circuit 2 switches in response to a selection signal SEL selecting a source line SL or a word line WL, and outputs the high voltage HV generated by the high voltage generation circuit 1. Sources of a plurality of memory cell transistors MT1, MT2, MT3 and so on are commonly connected to the source line SL, and control gates of the plurality of memory cell transistors MT1, MT2, MT3 and so on are commonly connected to the word line WL. When data is written (programmed), a first transfer gate 3 is turned on and a second transfer gate 4 is turned off to apply the high voltage HV to the source line SL. When the data is erased (the program is erased), the first transfer gate 3 is turned off and the second transfer gate 4 is turned on to apply the high voltage HV to the word line WL.
When the number of the memory cell transistors MT1, MT2, MT3 and so on in which data is simultaneously written increases, however, a writing current in a high voltage supply path, i.e. in the high voltage switching circuit 2 and the first transfer gate 3 increases and thus a voltage drop (an IR drop) increases by the increase amount, so that the number of the memory cell transistors in which data is simultaneously writable is limited. On the other hand, for reducing the voltage drop in the high voltage supply path, the transistors forming the high voltage switching circuit 2 and the first transfer gate 3 need be designed to have large sizes for lowering those impedances, thereby causing a problem of a large circuit area.